IEC 61523-2 Ed. 1.0 en:2002
Original price was: $163.00.$81.00Current price is: $81.00.
Delay and power calculation standards – Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries
International Electrotechnical Commission , 05/17/2002
Pages: 38
Applies to CMOS ASIC libraries which contain cell based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification and logic synthesis.The delay calculation method addressed in this standard consists of 1) estimation of wire capacitance 2 ) Delay calculation method based on tablelook-up. With use of DCL and SDF, this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.
Related products
Original price was: $51.00.$25.00Current price is: $25.00.
Original price was: $109.00.$54.00Current price is: $54.00.
Original price was: $28.00.$14.00Current price is: $14.00.
Original price was: $31.00.$15.00Current price is: $15.00.
Original price was: $117.00.$58.00Current price is: $58.00.
Original price was: $278.00.$139.00Current price is: $139.00.
Original price was: $278.00.$139.00Current price is: $139.00.
Original price was: $95.00.$47.00Current price is: $47.00.