IEC 62530 Ed. 1.0 en:2007
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Standard for SystemVerilog – Unified Hardware Design, Specification, and Verification Language
International Electrotechnical Commission , 11/07/2007
Pages: 663
Specifies extensions for a higher level of abstraction for modeling and verification with the Verilog hardware description language (HDL). This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI)>
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